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A Cornell Engineering Project Team dedicated to undergraduate semiconductor design

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C2S2 Blogs

Chip Gallery

Using CNF's optical microscopy, we can see a sailing ship design, that was added by our manufacturer Efabless, embedded in the metal layers of our digital chip, Eagle. Located among the standard cells and metal fill patterns, this microscopic artwork demonstrates how artistic elements can be integrated into functional IC layouts.

CNF Chip Art

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This test chip, developed by the ECE 5745 class, is designed to explore the capabilities of Caravel and OpenLane. At its core, the chip features a RISC-V Litex SoC architecture, enabling flexible and efficient processing. It integrates four specialized hardware accelerators to enhance performance in various applications: Group 15: Wavelet Compression Accelerator, Group 16: SpMV Accelerator, Group 17: BNN Accelerator, Group 99: GCD Accelerator

Dove ECE 5745 Spring'22

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The 2023 C2S2 Digital Tapeout showcases a design centered around a RISC-V Litex System on Chip. This chip features a custom digital Cooley-Tukey Fast Fourier Transform (FFT) implementation, optimized for high-speed signal processing tasks. The RISC-V architecture provides a flexible and scalable processing platform, enabling efficient execution of complex algorithms and data manipulation.

Eagle Digital Spring'23

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The 2023 C2S2 Analog Tapeout features an innovative hardware design centered around a RISC-V Litex System on Chip (SoC). This versatile chip incorporates multiple analog components to enhance its functionality: operational amplifiers - integrated to provide versatile analog signal processing capabilities, â€œfingers" implementation - allows for efficient interfacing and control in various analog scenarios, and â€œmultiplier" implementation - facilitates analog multiplication processes for applications requiring signal modulation and other complex mathematical operations.

Sparrow Analog Spring'23

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